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# Ve311 Homework #6

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Ve311 Homework #6

Note:
(1) Please use A4 size papers.
(2) Please use the SPICE model in page 3 for simulation and calculation.
(a) [30%] Assume λ = 0 and γ = 0. For VDD = 5 V, VIN = 0.9 V,
(Wdrawn/Ldrawn)2 = 5 µm / 2 µm and (Wdrawn/Ldrawn)1 = x µm / 2 µm, what is
the value of x to obtain a voltage gain Av = –5? What is the range of VIN
for M1 to stay in the saturation region?
(b) [10%] Using the design and biasing condition in (a), plot VOUT as a
function of VIN (from 0 V to 5 V) in Pspice. Compare the handcalculation results in (a) with the simulation results here. Note: the slope
of the VOUT versus VIN curve at VIN = 0.9 V is the Av
.
(c) [10%] Using the design and biasing conditions in (a), plot Vout as a
function of time (from 0 to 0.1 second) in Pspice, when Vin = 0.9 +
0.001 × sin(2π100t) (V). Compare the hand-calculation results in (a)
with the simulation results here. Note: the small-signal voltage amplitude
of Vout divided by the small-signal voltage amplitude of Vin is the Av
.
2
(a) [30%] Assume λ = 0 and γ = 0. For VDD = 5 V, VIN = 1.2 V,
(Wdrawn/Ldrawn)1 = 200 µm / 2 µm, RD = 100 kΩ and RS = 20 kΩ, what is
the voltage gain Av? Does the voltage gain approach –RD / RS as expected?
(b) [10%] Using the design and biasing condition in (a), plot VOUT as a
function of VIN (from 0 V to 5 V) in Pspice. Compare the handcalculation results in (a) with the simulation results here. Note: the slope
of the VOUT versus VIN curve at VIN = 1.2 V is the Av
.
(c) [10%] Using the design and biasing conditions in (a), plot Vout as a
function of time (from 0 to 0.1 second) in Pspice, when Vin = 1.2 +
0.001 × sin(2π100t) (V). Compare the hand-calculation results in (a)
with the simulation results here. Note: the small-signal voltage amplitude
of Vout divided by the small-signal voltage amplitude of Vin is the Av
.
3
Vacuum permittivity (𝛜𝐨) = 𝟖. 𝟖𝟓 × 𝟏𝟎−𝟏𝟐 (F / m)
Silicon oxide dielectric constant (𝛜𝐫
) = 𝟑. 𝟗

Ve311 Homework #6
\$30.00
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